Research
Please visit the above links to have a more detailed look at our research projects. Below is a list of Centers that we are leading or affiliated with.
NSF MBM at UIUC - Miniature Brain Machinery
NSF STC EBICS at MIT/GT/UIUC - Emergent Behavior of Integrated Cellular Systems
NSF IGERT at UIUC - Cellular and Molecular Mechanics and Bionanotechnology
(download brochure)NIH Training Grant at UIUC - Midwestern Cancer Nanotechnology Training Center
(download brochure)NSF CiiT (I/UCRC) at UIUC - Center for Innovative Instrumentation Technology
NSF NSEC at OSU - Center for Affordable Nanoengineering for Polymeric Micro and Nanodevices
Research:
Advanced Device Isolation for ULSI:
Silicon devices need to be isolated from each other in an integrated circuit chip. It is becoming increasing difficult to scale isolation processes in the deep-sub micron device isolation regions. The standard isolation techniques such as LOCOS (local oxidation of silicon) suffers from bird's beak encroachment and related problems. Poly buffered LOCOS has been used to minimize the encroachment of the oxide birds' beak. LOCOS based isolation techniques are being replaced with STI (Shallow trench isolation). In this process, trenches are etched, filled with oxide and then the oxide is planarized to form the field oxide regions.
Selective epitaxial growth is a very useful technology applied to make various advanced MOS, Bipolar, and BiCMOS structures. Selective epitaxial growth of silicon has been proposed to be used as isolation technologies. The potential of scalability and simplicity of the process makes it an ideal candidate as an advanced isolation process. Prior work has shown the feasibility of such a technique. The research will involve the use of selective epitaxial growth of silicon and chemical mechanical polishing to form device isolation regions scalable for deep sub-micron device isolation.
References:
[1] R. Bashir, G. W. Neudeck, H. Yen, E. P. Kvam, "Characterization of Sidewall Defects in Selective Epitaxial Growth of Silicon", Journal of Vacuum Science and Technology-B, Vol. 11, no. 5, pp. 1903-1905, June/July 1995.
[2] R. Bashir, G. W. Neudeck, H. Yen, E. P. Kvam, "Characterization and Modeling of Sidewall Defects in Selective Epitaxial Growth of Silicon", Journal of Vacuum Science and Technology-B, Vol. 11, no. 5, pp. 1903-1905, June/July 1995.
[3] J. M. Sherman, G. W. Neudeck, J. P. Denton, R. Bashir, W. W. Fultz, “Elimination of the Sidewall Defects in Selective Epitaxial Growth (SEG) of Silicon for a Dielectric Isolation Technology", IEEE Electron Device Letters, Vol.17, No. 6. June 1996.
[4] R. Bashir, Tai-chi Su, G. W. Neudeck, and J. P Denton , “Reduction of Defect Induced Leakage Currents by the Use of Nitrided Field Oxides in Selective Epitaxial Growth (SEG) Isolation for Silicon ULSI”, 41st Electronic Materials Conference, Santa Barbara, CA, June 30th-July 2nd, 1999. [abstract (pdf)]